1. Field of the Invention
The present invention relates to a derivative superposition circuit for linearization, in which transistors having a different gate length, which are supported in a general CMOS process, are used so that stable linearization is possible without delicate tuning, and a plurality of transistors can be operated only by one bias voltage so that a bias circuit can be easily constructed and the overall area of the circuit can be reduced.
2. Description of the Related Art
Recently, wireless communication systems with various purposes are commonly used through standardization. Accordingly, such a phenomenon increases where undesired signals are interfered with each other.
Further, the communication systems use a different frequency range. Therefore, if all the systems are perfectly linearized, the respective systems can communicate without being interfered with each other. However, since transmitters and receivers which are used in most of real communication systems are implemented of non-linearized circuits, such problems occur, which are caused by the mixture and modulation between signals generated while the signals pass through the non-linearized systems. Particularly, a third-order intermodulation distortion (hereinafter, referred to as IMD3) signal, which is generated when two strong signals in an adjacent frequency range are mixed while passing through non-linearized systems, distorts a desired signal in the operational frequency range of a system. Therefore, a third-order intercept point (hereinafter referred to as IP3) is defined so as to be used as an index representing the linearization of system.
As such, various studies for improving such linearization are being carried out, while the linearization of system is emphasized. Recently, a derivative superposition method is frequently used, which can improve IP3 of a CMOS low-noise amplifier.
FIG. 1 is a circuit diagram showing a derivative superposition circuit 100 according to a related art. As shown in FIG. 1, the derivative superposition circuit 100 includes a first MOSFET 101 and a second MOSFET 102 which has complementary characteristics with the first MOSFET 101.
The gates of the first and second MOSFETs 101 and 102 are connected to an input end IN through a first impedance 10, the drains of the first and second MOSFETs 101 and 102 are connected to an output end, and the sources of the first and second MOSFETs 101 and 102 are connected to a ground power supply 105 through a third impedance 108.
In the gate of the first MOSFET 101, a predetermined operational bias voltage is maintained by a gate-to-source voltage (VGS) 103 and a ground power supply 105 through a first resistance 106a of the first impedance 106. In the gate of the second MOSFET 102, a predetermined operational bias voltage is maintained by the gate-to-source voltage (VGS) 103 and an offset voltage (Voff) 105 through a second resistance 106b of the first impedance 106.
FIG. 2 is a graph showing simulation results of a second derivative gm″ of trans-conductance with respect to the gate-to-source voltage VGS according to the related art.
As an offset voltage is applied to the gate of the second MOSFET so as to adjust an operational bias voltage of the second MOSFET, the maximum value region of the second derivative gmA″ of trans-conductance of the first MOSFET and the minimum value region of the second derivative gmB″ of trans-conductance of the second MOSFET have an opposite sign, as shown in FIG. 2. Accordingly, the IMD3 signals generated by two MOSFETs are offset around the threshold voltage of the first and second MOSFETs, which makes it possible to obtain a second derivative gm″ of trans-conductance which is further linearized.
FIG. 3 is a circuit diagram showing a derivative superposition circuit according to another related art. FIGS. 4A to 4C are graphs showing simulation results of a second derivative gm″ of trans-conductance with respect to a gate-to-source voltage VGS according to the related art.
FIG. 3A shows a derivative superposition circuit including a first MOSFET M1 which is operated by a constant gate-to-source bias voltage VGS and a derivative superposition circuit including a second MOSFET M2 which is operated by a bias voltage (VGS−VB1) in which a predetermined voltage VB1 (=0.3V) is subtracted from the gate-to-source bias voltage VGS. FIG. 3B shows a derivative superposition circuit in which the first and second MOSFETs, commonly connected to a signal input end, are connected to each other and a derivative superposition circuit including a third MOSFET M3 which is operated by a bias voltage (VGS−VB2) in which a predetermined voltage VBs (=0.53V) is subtracted from the gate-to-source bias voltage VGS. FIG. 3C shows a derivative superposition circuit in which the first, second, and third MOSFETs, commonly connected to a signal input end, are connected to each other.
When the peak value of the second derivative of trans-conductance is positive as shown in FIGS. 4A and 4B, a negative value of the second derivative of trans-conductance of the derivative circuit including the first MOSFET M1 or the derivative circuit in which the first and second MOSFETs M1 and M2 are connected is offset by a positive value of the second derivative of trans-conductance of the second MOSFET M2 or the third MOSFET M3. As a MOSFET having an adequate size and bias voltage is added, a linearized region is increasingly expanded as shown in FIG. 4C.
In the above-described derivative superposition circuit according to the related art, however, the offset voltage Voff of FIG. 1 or the predetermined voltages VB1 and VB2 of FIG. 3 should be adjusted through delicate tuning, in order to perform stable linearization.
Further, since a bias circuit which controls the offset voltage Voff of FIG. 1 or the predetermined voltages VB1 and VB2 of FIG. 3 should be added, constructing a bias circuit is not only easy, but the overall area of the circuit is also widened.